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Trekno - High-Performance Trekking Gear, Essential Outdoor Equipment
Trekno - High-Performance Trekking Gear, Essential Outdoor Equipment Trekno - High-Performance Trekking Gear, Essential Outdoor Equipment
Home Trekking Gear Insulating Layers
Source-Drain Deposition Mask, Low Density
Source-Drain Deposition Mask, Low Density
DesignType:
  • 30micronchannellength
  • variablechannellength

$ 75.65

$ 58.19

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Product Details

Produce a total of 60 devices in a single evaporation

ensures conductivity between the metal electrodes and the p-doped silicon


Shadow masks for deposition of source drain contacts. Designed for use in the with our standard sized substrates of 20 x 15 mm. Each mask will work with up to 12 substrates, each with five OFETs to produce a total of 60 devices in a single evaporation.

Datasheet


Linear channels of width 1 mm with two designs available of either five identical channel lengths of 30 μm or variable channel lengths of 30, 40, 50, 60 and 80 μm (one per substrate)

Number of OFETs60 (5 per substrate)
Channel lengthE291: 30 μm
E292: 30, 40, 50, 60, 80 μm (one each per substrate)
Channel width1 mm
Contact pad size1 mm x 1 mm
Mask thickness35 µm
Channel bar tolerance±10 µm
Mask materialHard electroformed nickel

*E291/E292 yield of working devices is 90% (54/60).

Schematic of the the whole mask (see source-drain evaporation stack for details of how it fits with other layers).
Optical image of the variable width source-drain evaporation mask.
Optical image of the 30 µm width source-drain evaporation mask

The mask is designed in such a way that during the deposition of the gate electrodes on the corner of the substrate the metal should cover the edge of the substrate as well. This ensures conductivity between the metal electrodes and the p-doped silicon. If you find the edges of the substrate not to be conductive you must scratch the edges of the substrate to remove the insulating silicon oxide in correspondence with the corner where the gate electrode will be deposited.

Prefabricated OFET: details of the gate pad/doped silicon electrical contact.
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